1. Field of the Invention
The present invention relates to a decoder circuit of a semiconductor storage device. In particular, the present invention relates to a decoder circuit of an electrically rewritable non-volatile semiconductor storage device.
2. Description of the Related Art
In a conventional non-volatile semiconductor storage device, such as a flash memory, a high-voltage transistor is incorporated therein, since the conventional non-volatile semiconductor storage device has to be applied with a high voltage when performing writing or erasing of data. However, it is necessary to increase the thickness of a gate oxide film and the length of a gate of the transistor to withstand a high voltage, which may deteriorate a driving force of the transistor.
Japanese Patent Application Laid-Open (JP-A) No. 11-185489 discloses an X-decoder circuit that selects a word line by switching between a high-voltage driver circuit and a low-voltage driver circuit. This X-decoder circuit uses the high-voltage driver circuit when a high voltage is necessary, such as when writing or erasing data, and uses the low-voltage driver circuit when a high voltage is not necessary, such as when reading data. Due thereto, this X-decoder circuit prevents an operation speed from being lowered when a high voltage is not necessary.
However, this X-decoder circuit has to include not only the high-voltage driver circuit but also the low-voltage driver circuit, which may increases the circuit area of the X-decoder circuit.
JP-A No. 2007-310936 discloses a row decoder including a driver circuit in which a high-voltage transistor is used.
However, this row decoder also uses the high-voltage transistor. Therefore, this row decoder may not perform an operation at high speed and the circuit area of the driver circuit may increase.
FIG. 13 is a diagram illustrating an example of a conventional row decoder 100. A row decoder 100 shown in FIG. 13 selects a word line with reference to the address of a memory cell to be accessed, when accessing to the memory cell. The row decoder 100 applies a normal voltage to the selected word line when reading data, and applies a high voltage to the selected word line when writing or erasing data.
As shown in FIG. 13, the row decoder 100 includes a level shift circuit 102 and a word line selection circuit 104. The level shift circuit 102 includes high-voltage PMOS transistors P101 and P102, NMOS transistors N101 to N104, and an inverter 106. The word line selection circuit 104 includes a high-voltage PMOS transistor P103, high-voltage PMOS transistors P200 to P20n disposed for each signal HVXPB [n:0] respectively, and NMOS transistors N300 to N30n, N400 to N40n, and N500 to N50n disposed for each signal XPB [n:0] respectively.
FIG. 14 is a chart illustrating the voltage values of the respective signals in a normal operation (NORMAL) that uses a normal voltage when reading data, and in a high voltage operation (HV) that uses a high voltage when writing or erasing data, in selection and non-selection of the word lines. FIG. 15A is a diagram illustrating a timing chart of the respective signals in the normal operation. FIG. 15B is a diagram illustrating a timing chart of the respective signals in the high voltage operation.
VPP shown in FIG. 14 is a high voltage supplied from an external power supply (not shown). An example of VPP is 10.0 [V]. VCC is a voltage supplied from the external power supply (not shown). Examples of VCC are 3.0 to 4.0 [V]. VCW is a voltage supplied from an internal power supply (not shown) and an example of VCW is 3.6 [V]. VNN is a ground potential and an example of VNN is 0.0 [V].
SLCT is a signal that becomes “H” (high level: VCC) when any one of the word lines WL [n:0] is selected, irrespective to the normal operation or the high voltage operation. The signal SLCT becomes “L” (low level: 0 V) when none of the word lines is selected, irrespective to the normal operation or the high voltage operation.
When the signal SLCT becomes “H”, HVXPB [n:0] corresponding to the selected word line number becomes 0.0 [V] irrespective to the normal operation and the high voltage operation. Accordingly, in the normal operation, 3.6 [V] is supplied to the corresponding word line WL. Thus, in the high voltage operation, 10.0 [V] is supplied to the corresponding word line WL.
HV_SLCTB is a signal that becomes “H” (VCW in the normal operation and VPP in the high voltage operation) in the non-selection of the word line.
XPB is a signal that becomes “L” when a word line is selected, and becomes “H” when the word line is not selected, irrespective to the normal operation or the high voltage operation.
VWLX is a signal that becomes VCW in the normal operation, and becomes VPP in the high voltage operation, irrespective to the selection or the non-selection of a word line.
Hereinafter, an operation for selecting the word line WL0 and supplying VCW to the word line WL0 will be described as an example for the selecting a word line in the normal operation.
In this case, SLCT=“H”, HVXPB [0]=0.0 [V], XPB [0]=“L”, HVXPB [n:1]=VCW=3.6 [V], and XPB [n:1]=“H” are input. Here, n is a positive integer, and HVXPB [n:0] and XPB [n:0] correspond to n+1 lines of word lines WLn to WL0.
In this case, the level shift circuit 102 shifts the input SLCT=“H”=VCC to HV_SLCTB=“L”=0.0 [V], and outputs the shifted signal to the word line selection circuit 104.
The inverse signal of SLCT=“H” is input to the gates of the NMOS transistors N500 to N50n of the word line selection circuit 104 by the inverter 106. Accordingly, all the NMOS transistors N500 to N50n become a non-conductive state.
When the word line WL0 is selected, HV_SLCTB is “L” and HVXPB [0] is “L”, and the high-voltage PMOS transistors P103 and P200 are in a conductive state. Further, the NMOS transistor N300 are in a non-conductive state based on XPB [0]=“L”. Accordingly, the word line WL0 is connected to VWLX=VCW=3.6 [V] and is disconnected from VNN=0.0 [V], and, therefore, WL0 becomes VCW=3.6 [V]. Since the other word lines WL are disconnected from the signal VWLX based on HVXPB [n:1]=VCW=3.6 [V] and XPB [n:1]=“H” and are connected to the signal VNN, WL [n:1] become 0.0 [V].
When SLCT=“H”, HVXPB [n:0]=0.0 [V], and XPB [n:0]=“L”, all the word lines WL [n:0] may be selected, as in the above-described case of the selection of the word line WL0. Accordingly, WL [n:0] become VCW=3.6 [V].
Next, an operation when none of the word lines WL [n:0] is selected, will be described. In this case, SLCT=“L” is input. For HVXPB [n:0], input of VCW=3.6 [V] or VCW=0.0 [V] is allowed, and for XPB [n:0] an arbitrary input value of “H” or “L” is allowed.
When SLCT is “L”, HV_SLCTB become “H”=3.6 [V]. Due thereto, the high-voltage PMOS transistor P103 becomes a non-conductive state. On the other hand, all the NMOS transistors N500 to N50n, into which the inverse signal of the signal SLCT is input, become a conductive state. Thus, since the word lines WL [n:0] are disconnected from the signal VWLX, and are connected to the signal VNN, WL [n:0] become 0.0 [V].
Next, an operation for selecting the word line WL0 and supplying VPP=10.0 [V] to WL0 will be described, as an example for the selecting a word line in the high voltage operation. In this case, SLCT=“H”, HVXPB [0]=0.0 [V], XPB [0]=“L”, HVXPB [n:1]=VPP=10.0 [V], and XPB [n:1]=“H” are input.
The level shift circuit 102 shifts SLCT=“H”=VCC to HV_SLCTB=“L”=0.0 [V] and outputs the shifted signal to the word line selection circuit 104, as in the normal operation.
The inverse signal of SLCT=“H”, inverted by the inverter 106, is input to the gates of the NMOS transistors N500 to N50n of the word line selection circuit 104. Therefore, all the NMOS transistors N500 to N50n become a non-conductive state.
When the word line WL0 is selected, HVXPB [0] is “L”, XPB [0] is “L”, HVXPB [n:1] are VPP=10.0 [V], and XPB [n:1] are “H”. Thus, the high-voltage PMOS transistors P103 and P200 become a conductive state based on HV_SLCTB=0.0 [V] and HVXPB [0]=0.0 [V]. The NMOS transistor N300 becomes a non-conductive state based on XPB [0]=“L”. Due thereto, the word line WL0 is connected to VWLX=VPP=10.0 [V] and is disconnected from VNN=0.0 [V]. Accordingly, WL0 becomes VPP=10.0 [V]. Since the other word lines WL are disconnected from the signal VWLX based on HVXPB [n:1]=VPP=10.0 [V] and XPB [n:1]=“H” and are connected to the signal VNN, WL [n:1] become 0.0 [V].
Note that when SLCT=“H”, HVXPB [n:0]=0.0 [V], and XPB [n:0]=“L”, all the word lines WL [n:0] may be selected, as in the above-described case of the selection of the word line WL0. Accordingly, WL [n:0] become VPP=10.0 [V].
Next, an operation for selecting none of the word lines WL [n:0] will be described. In this case, SLCT=“L” is input. For HVXPB [n:0], VPP=10.0 [V] or VPP=0.0 [V] may be input, and for XPB [n:0] an arbitrary input value of “H” or “L” may be input.
By inputting SLCT=“L”, HV_SLCTB becomes “H”=10.0 [V]. Therefore, the high-voltage PMOS transistor P103 becomes a non-conductive state. On the other hand, all the NMOS transistors N500 to N50n, into which the inverse signal of the signal SLCT is input, become a conductive state. Thus, since the word lines WL [n:0] are disconnected from the signal VWLX, and is connected to the signal VNN, WL [n:0] become 0.0 [V]. FIG. 16 is a diagram illustrating the voltage state of the selection of a word line in the high voltage operation. Further, FIG. 17 is a diagram illustrating the voltage state of the non-selection of a word line in the high voltage operation.
As shown in FIG. 16 and FIG. 17, in the conventional row decoder 100, the high voltage in the range from 0.0 [V] to 10.0 [V] is applied to the electrodes of the PMOS transistors P101 and P102 of the level shift circuit 102, and the PMOS transistors P103, P200, P201, . . . , P20n of the word line selection circuit 104. Therefore, in the conventional row decoder 100, these transistors have to resist the high voltage. Accordingly, the conventional row decoder 100 may not perform an operation at high speed and the circuit area of the driver circuit may increase.